The invention relates generally to storage device and an access instruction sending method, and is suitable for application in, for example, a storage device having an arbiter allowing exclusive access by arbitrating between accesses from plural processors.
Currently, when a plurality of bus masters connected to a bus operate by sharing the bus, a bus master requests a usage right; acquires a bus right; and then uses the right. The bus usage right is managed by a bus arbiter (an arbiter), and with respect to requests for bus usage rights from the bus masters, the bus arbiter provides the bus usage right in the appropriate order of priority.
As an example of a technique of this sort, there is a system having a bus supporting a split transaction in order to improve bus efficiency, in which a bus is used effectively by optimizing the number of DMA command buffer layers in accordance with the number of received buffer layers on a bus slave side (for example, see JP10-011387 A).